1. Field of the Invention
The present invention relates to methods of manufacturing semiconductor devices, and more particularly, to methods of manufacturing semiconductor devices, which can reduce hot electron induced punch-through (HEIP) and/or improve operating characteristics of the semiconductor device.
2. Description of the Related Art
In general, semiconductor devices can include an active region in which unit devices are formed, and a device isolation region that defines the active region. The device isolation region can account for a large proportion of a total area of semiconductor devices, and thus miniaturization of the device isolation region can be desired for high integration of semiconductor devices. In addition, in order to ensure that devices operate properly, a device isolation region can have a structure that can reduce or prevent interference between devices and/or decrease junction capacitance. In the past, a local oxidation of silicon (LOCOS) type oxide layer was used as a device isolation layer in semiconductor devices, but currently, shallow trench isolation (STI) type device isolation layers, that can have a narrow width and excellent device isolation properties, are widely used.
FIG. 1 is a schematic cross-sectional view of a semiconductor device including a conventional STI type device isolation layer.
Referring to FIG. 1, device isolation layers 2 are formed in a substrate 1. An active region 3 including a source/drain region and a channel region is formed between the device isolation layers 2, and a gate structure 9 is formed on the active region 3. Such device isolation layers 2 are formed as trenches filled with insulating material, and thus electrically separate the devices from each other. As illustrated in FIG. 1, in order to improve refresh characteristics of a semiconductor device, a silicon oxide layer 4 and a silicon nitride layer 6 are generally formed on inner walls of a device isolation layer trench. And then, the device isolation trench is filled with a buried layer 8 having a gap fill material such as spin-on-glass (SOG).
However, the silicon nitride layer 6 may trap electrons, and thus electrons may be trapped at an interface between the silicon oxide layer 4 and the silicon nitride layer 6. As a result of the trapped electrons, holes can become concentrated in a region of the substrate 1 adjacent to the device isolation layer 2. This can lead to a phenomenon referred to as hot electron induced punch-through (HEIP). Due to HEIP, current can flow in a device even when a voltage is not applied to a gate, and thus a threshold voltage can be decreased and leakage current can be increased, potentially resulting in defective devices. Such a HEIP phenomenon can be especially problematic in a p-channel metal-oxide-semiconductor (p-MOS) devices in which holes are the major carrier and a programming voltage Vpp is applied at a high voltage. In particular, off-current characteristics of a device can be degraded. To address these problems, a method of removing the nitride layer from a device isolation layer of a p-MOS device has been proposed in order to reduce/prevent electrons from becoming trapped in a silicon nitride layer. However, when etching is used for removing the nitride layer, other layers of the device may be damaged.